1. Field of the Invention
The present invention relates to method of synchronizing clock and device for use in such method to output data inputted in synchronization with a first clock in synchronization with a second clock which can be used suitably, for example, for a computer network.
2. Description of the Related Art
In some of conventional local area networks (LAN), as shown in FIG. 12, personal computers 311 and 312 are connected through packet assembling and disassembling devices 321 and 322, interfaces 331 and 332 and packet sending/receiving devices 341 and 342 to a network 35 of LAN. In LANs, a packet is used to send or receive data between a personal computer and the network 35 of LANs.
In some cases of transmission of packets, though there is no difference in frequency between a clock signal of an input packet and that of an output packet, a variation exists between a frequency of the clock signals of the input packet and that of the output packet. Also, in some cases, even if there is the difference as described above, there is a variation between a frequency of the clock signal of the input packet and that of the output packet. In such a case, in order to correctly pass an inputted packet to an output side, it is vital to output data inputted in synchronization with the input clock in synchronization with the output clock (i.e., it means that a clock of data is converted from the input clock to the output clock). However, in the case of sequence data such as a packet, a conversion of a clock is impossible by detection of a rise or fall of a pulse due to omission or duplication of data.
Because of this, as shown in FIG. 13, packet assembling/disassembling devices 321 and 322 of a LAN are provided with a clock synchronizing circuit used to convert a clock. As depicted in FIG. 13, the clock synchronizing circuit contains a memory 42, a write pointer generating circuit 45, a data termination detecting circuit 46 and a read pointer generating circuit 47. At the start of the conversion of a clock, the memory 42 is initialized and, at the same time, the write pointer generating circuit 45 initializes a write pointer in response to an input clock and generates an initialized write pointer, while the read pointer generating circuit 47 initializes a read pointer in response to an output clock and generates an initialized read pointer (Step SQ1 and SQ2 in FIG. 14). Until a packet data is inputted to a write input of the memory 42, the generated write pointer is not renewed (Step SQ3). When the packet data is inputted (Step SQ3), the memory 42 writes, in response to the input clock signal, a write data unit out of the inputted packet data into a storage position designated by the write pointer outputted from the write pointer generating circuit 45 (Step SP4). Then, the write pointer is renewed (Step SQ5).
Every time the write pointer is renewed, a judgement on whether writing of all packet data is terminated or not is made by a data termination detecting circuit 46 (Step SQ6). If the writing is not terminated, a subsequent write data unit of the packet data is written into a write position of a memory 42 designated by the write pointer renewed by the write pointer generating circuit 45.
If the judgement on termination of writing the packet data is positive (in the case of xe2x80x9cYESxe2x80x9d of Step SQ6), a packet write termination instructing signal is generated (Step SQ7) and a signal for processing packet reading is fed and, at the same time, in the packet writing processing, the operation returns back to Step SQ3 which is in the waiting state for inputting of packet data and to wait for inputting of a subsequent packet data.
At the same time when the packet writing processing is in the state of waiting for packet data, reading processing that had been in the standby state is started in response to the packet writing termination instructing signal (in the case of xe2x80x9cYESxe2x80x9d in Step SQ8) When this packet reading processing is started, a read data unit of the packet is read from the reading position of the memory 42 designated by the read pointer that had been initialized (Step SQ9) and the read data unit is outputted as a first read data unit of the packet written in the memory 42. At the same when this reading is carried out, the read pointer is renewed to be a read pointer having a subsequent data unit (Step SQ10).
Every time such reading pointer is renewed, a judgement on whether reading of packet data is terminated or not is carried out (Step SQ11). If it is not terminated (in the case of xe2x80x9cNOxe2x80x9d in Step SQ11), a subsequent read data unit of packet data is read from a reading position of the memory 42 designated by the renewed read pointer.
If the judgement on termination of reading the packet data is positive (in the case of xe2x80x9cYESxe2x80x9d of Step SQ11), the operation returns back to Step SQ8 being in the standby state for the start of the packet reading and to wait for a packet writing termination instructing signal of the subsequent packet until a signal of informing the termination of writing the packet is received. Thus, the above procedure allows data inputted in synchronization with an input clock to be outputted in synchronization with an output clock (i.e., when data is inputted or outputted, a clock of data can be converted from the input clock to the output clock).
However, as described above, though the conventional synchronizing circuit allows packet data inputted in synchronization with an input clock to be outputted in synchronization with an output clock, in order to achieve the synchronization, only one technique is available wherein, after a whole packet is written into the memory 42 by an input clock signal having the number of writing units constituting one packet, the packet is read by the output signal having the number of reading units constituting the packet. However, this technique suffers a shortcoming that one packet of storage capacity is unavoidably required for outputting packet data inputted in synchronization with an input clock to be outputted in synchronization with an output clock, thus causing a delay of sending and receiving a packet caused by a temporary storage. Moreover, another disadvantage is that a major portion of a chip area is occupied by the synchronizing circuit in integration process on a semiconductor chip.
In view of the above, it is an object of the present invention to provide method of synchronizing clock and device for use in such method which allows a reduction in storage capacity required for outputting data inputted in synchronization with an input clock in synchronization with an output clock, thus achieving simplification, miniaturization and drop in prices of the synchronizing device.
According to a first aspect of the present invention, there is provided a method of synchronizing a clock for transferring data from a first circuit operated at a first clock through a storing means being accessible independently to its input and output to a second circuit operated by a second clock comprising the steps of:
storing data fed by the storing means;
detecting whether data stored in the storing means is effective data;
renewing, if a decision is positive, an access pointer of the storing means in response to the clock;
re-initializing, if a decision is negative, the access pointer of the storing means in response to the clock; and
outputting data inputted in synchronization with the first clock in synchronization with the second clock by accessing the storing means using the access pointer.
In the foregoing, a preferable mode is one wherein a frequency of first clock is different from that of second clock.
Also, a preferable mode is one wherein width of storage capacity N of the storing means is a sum of a width of storage capacity given by a following formula (1) derived in the case where an output clock is faster than an input clock and a width of storage capacity given by a following formula (2) derived in the case where the input clock is faster than the output clock;
N less than n+1xe2x80x83xe2x80x83(1)
xe2x80x83nxe2x89xa6Nxe2x80x83xe2x80x83(2)
where n=|Axe2x88x92B|xc3x97L/max (A, B), wherein A is a frequency of the first clock, B is a frequency of the second clock and L is a maximum packet length, and max (A, B) represents that max (A, B)=A if Axe2x89xa7B and max (A, B)=B if A less than B. N is an arbitrary natural number.
Also, a preferable mode is one wherein the re-initialization is performed only on the access pointer of the second circuit.
Also, a preferable mode is one wherein the re-initialization is performed only on the access pointer of the first circuit.
Furthermore, a preferable mode is one wherein the re-initialization is performed on the access pointers of both first and second circuits.
According to a second aspect of the present invention, there is provided a method of synchronizing a clock for transferring data from a first circuit operated at a first clock through a storage means being accessible independently to its input and output to a second circuit operated by a second clock comprising:
a storing means being accessible independently to its input and output;
a detecting means to detect whether data stored in the storing means is effective data;
an access pointer generating means to renew an access pointer of the storing means, when the detecting means shows a positive decision, in response to the clock and to reinitialize an access pointer of the storing means, when the detecting means shows a negative decision, in response to the clock; and
a means to output data inputted in synchronization with the first clock in synchronization with the second clock by accessing the storing means using the access pointer outputted from the access pointer generating means.
In the foregoing, it is preferable that a frequency of the first clock is different from that of the second clock.
Also, it is preferable that width of storage capacity N of the storing means is a sum of a width of storage capacity given by a following formula (3) derived in the case where an output clock is faster than an output clock and a width of storage capacity given by a following formula (4) derived in the case where the input clock is faster than the output clock;
N less than n+1xe2x80x83xe2x80x83(3)
nxe2x89xa6Nxe2x80x83xe2x80x83(4)
where n=|Axe2x88x92B|xc3x97L/max (A, B), wherein A is a frequency of the first clock, B is a frequency of the second clock and L is a maximum packet length, and max (A, B) represents that max (A, B)=A if Axe2x89xa7B and max (A, B)=B if A less than B. N is an arbitrary natural number.
Also, it is preferable that re-initialization of the access pointer using the access pointer generating means is performed only on the access pointer of the second circuit.
Also, it is preferable that re-initialization of the access pointer using the access pointer generating means is performed only on the access pointer of said first circuit.
Furthermore, it is preferable that the re-initialization of the access pointer using the access pointer generating means is performed on the access pointer of both first and second circuits.